Vedic Multipier

In: Computers and Technology

Submitted By ash007
Words 2343
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VHDL IMPLEMENTATION OF FLOATING POINT
MULTIPLIER USING VEDIC MATHEMATICS
I.V.VAIBHAV1, K.V.SAICHARAN1, B.SRAVANTHI1, D.SRINIVASULU2
1

Students of Department of ECE,SACET, Chirala, AP, India
Associate Professor of the Dept ECE, SACET, Chirala, AP, India
3
Electronics and Comunication Department, St.Ann‟s college of engineering & Technology, Chirala, india.
E-mail:innamurivaibhav1@gmail.com, kota.saicharan@gmail.com, sravanthi.408b@gmail.com, seenu_dasari@rediffmail.com 2

Abstract: This project presents a binary floating point multiplier based on Vedic algorithm. To improve power efficiency a new algorithm called URDHVA-TRIYAKBHYAM has been implemented for 24 X 24 bit multiplier design. By using this approach number of components can be decreased and complexity of hardware circuit can be decrease. In this project, Vedic multiplication technique is used to implement IEEE 754 floating point multiplier. The Urdhava-Triyakbhym sutra is used for the multiplication of Mantissa i.e., 24x24 bits. The sign bit of the result is calculated using one XOR gate and a Carry Save
Adder is used for adding the two biased Exponents. The underflow and overflow cases are handled. The inputs to the multiplier are provided in IEEE 754, 32 bit format. The multiplier is implemented in VHDL and Spartan3E FPGA is used.
The result consists of 32 bit binary number of which MSB represent sign, next 8 bit represents Exponent and remaining 23 bits represents Mantissa.
Keywords: Vedic Mathematics, Urdhva -Triyakbhyam sutra, Floating Point multiplier, Field Programmable Gate Array (
FPGA), Carry Save Adder

main aims of designing floating point units (FPUs) for reconfigurable hardware implementation are: (a) to parameterise the precision and range of the floating-point format to allow optimizing the FPUs for specific applications, and (b) to support optional inclusion of…...

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